1. Field of the Invention
The present invention relates to a semiconductor device and a wiring forming method in a semiconductor device and, more particularly to a semiconductor device in which a gap exists between wirings, and a wiring forming method in a semiconductor device.
2. Description of Related Art
In recent years, in a semiconductor device, multiple-layer wiring and miniaturization have been greatly advanced for the sake of higher performance. In a case of such a semiconductor device, as the miniaturization is advanced, parasitic capacitance between the wirings is increased, which leads to a serious problem for the development of a higher speed of a semiconductor device.
As a unit for reducing a drop in the parasitic capacitance, a technique of forming a gap between a plurality of wirings formed on a substrate is known (for convenience, it is referred to as a hollow wiring technique). The outline of an example of this hollow wiring technique will be described below with reference to sectional views of insulation layers of FIGS. 9A to 10B and the like, on the basis of a technique disclosed in Japanese Patent Application Laid-Open JP-A-Heisei, 2-240947.
[Process 10]
At first, a known transistor element (for example, MOS type FET) is formed on a semiconductor substrate. Then, a first insulation layer 110 is formed on the entire surface by using a CVD method. After that, for example, a lithography technique and a dry etching technique are used to form openings on the first insulation layer 110. Then, for example, a sputtering technique and the dry etching technique are used to fill wiring material into the opening. Also, first wirings 111 are formed on the first insulation layer 110. This situation is shown in FIGS. 9A and 9B. However, the illustrations of the semiconductor substrate, the transistor element and the openings are omitted in FIGS. 9A to 10B. Also, FIGS. 9A and 9C and FIG. 10A are the views when the first insulation layer 110 and the like are cut on a plane vertical to a direction orthogonal to a direction in which the first wiring 111 is extended, and FIGS. 9B and 9D and FIG. 10B are the views when the first insulation layer 110 and the like are cut on a plane vertical to a direction parallel to the direction in which the first wiring 111 is extended.
[Process-20]
After that, after a second insulation layer 112 is formed on the entire surface by using the CVD method, planarization is performed on a surface of the second insulation layer 112. Next, the lithography technique and the dry etching technique are used to form the openings on the second insulation layer 112 above the first wiring 111. Next, for example, the sputtering technique and the dry etching technique are used to fill the wiring material into the openings. Also, second wirings 113 are formed on the second insulation layer 112. This situation is shown in FIGS. 9C and 9D.
[Process-30]
Next, the second wiring 113 is used as an etching mask, and the second insulation layer 112 is etched. Accordingly, gaps 114 can be formed between the first wirings 111 and between the second wirings 113. This situation is shown in FIGS. 10A and 10B. After that, thin insulation layer is formed on the entire surface, and the wiring structure is completed.
Also, a semiconductor device having a structure in which the gap between a plurality of wirings formed on the substrate is vacuum is also well known.
Such a hollow wiring technique is effective means for dropping the parasitic capacitance between the wirings. However, since the gap is filled with air or it is vacuum, this results in a problem that the thermal diffusion in the gap is poor. That is, the heat generation when the semiconductor device is operated causes the wiring to be deformed or cut away, and also brings about drop in reliability and occurrence of a trouble in the semiconductor device.
Therefore, the present invention provides a semiconductor device, in which the problem such as the defect of the thermal diffusion in the hollow wiring technique can be solved, and a wiring formation method in a semiconductor device.